1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device formed from adjacent dice on a semiconductor wafer.
2. State of the Art
Electrical components and circuits have been manufactured for some time in the form of integrated circuits fabricated on wafers of semiconductor materials. Formation of integrated circuits on a semiconductor wafer utilizes various techniques such as etching, doping, and layering for forming active circuits and interconnects. Individual integrated circuits on a wafer are referred to as dice and provide an interface for coupling with external electrical connections. Generally, a die on a wafer is separated from other dice by cutting the wafer along scribe or segmentation lanes thereby forming individual integrated circuit “chips” that may be subsequently packaged for use. Because of the increased integration and miniaturization of electronic systems, a need has arisen for identifying higher density approaches for packaging integrated circuits.
One approach for improving packaging density of integrated circuits has been to place chips on a circuit board in a vertically stacked arrangement. In such approaches, chips are generally packaged and then the individual packages are stacked in a vertical arrangement. Vertical package approaches have utilized an intricate and sophisticated cross-wiring approach which modifies the individual chips so that they may be stacked by adding a pattern of metallization, often called rerouting leads, to the surface of the wafer. Such rerouting leads extend from the bond pads of the chip to newly formed bond pads that may be arranged along the terminating edge of the chip. In such a configuration, each modified chip is then cut from the wafer and assembled into a stack such that all of the leads of the modified chips are aligned along the same side of the stack resulting in a vertical interconnection of the individual chips. Such approaches result in only modest volumetric improvements at a great interconnection expense that presents many opportunities for failure as well as requires intricate assembly approaches.
Other approaches for arraying or otherwise assembling multiple integrated circuits in a more volume-efficient approach include the formation of memory modules which are formed from individual dice that are assembled individually on a common printed circuit board with each of the pads from an individual die routed to the external printed circuit board which provides the interconnection to an adjacent die or dice. While such an approach reduces the number of packages per die, as a plurality of dice are placed on a single printed circuit board and then packaged into a larger memory module assembly, such an approach still results in significant spacing between each of the individual dice in order to accommodate manufacturing processes for externally coupling die pads from one integrated circuit to adjacent integrated circuits. Therefore, there is a nee for providing an improved and volumetrically more efficient coupling of integrated circuit chips without incurring significant expense of assembling and interconnecting multiple dice for use in higher assembly package.